Semiconductor device

ABSTRACT

In a semiconductor device with ferroelectric capacitors, variations in the characteristics of the ferroelectric capacitors are reduced, and changes in the characteristic of the ferroelectric capacitor, i.e., characteristic deterioration with passage of time, is suppressed. Lower electrodes 111a that extend along a first direction D1 and have a plan configuration having a second direction D2 perpendicular to the first direction as its width direction, a plurality of upper electrodes 112a that are disposed on the lower electrodes 111a opposite to the lower electrodes, and ferroelectric layers that are disposed between the electrodes constitute ferroelectric capacitors 110a, and a plan configuration of the upper electrode 112a is made a shape of the size in the first direction D1 being smaller than the size in the second direction D2.

TECHNICAL FIELD

The present invention relates to a semiconductor device and, moreparticularly, to improvements in variations in characteristics andcharacteristic deterioration in a ferroelectric memory device.

BACKGROUND ART

As conventional semiconductor devices, there have been developed variouscircuits from relatively small-sized integrated circuits mounting, forexample, an amplifier circuit, an oscillating circuit, a power supplycircuit and the like, to relatively large-sized integrated circuits,such as a microprocessor and a memory device. Especially in recentyears, as a kind of non-volatile memory device, a ferroelectric memorydevice with ferroelectric capacitors as capacitors constituting memorycells has been contrived.

The ferroelectric capacitor consists of a pair of electrodes opposite toeach other, and a dielectric layer comprising a ferroelectric materialand sandwiched between both electrodes, and has the hysteresischaracteristic as a relationship between a voltage applied between theboth electrodes and polarizability of the ferroelectric material. Thatis, the ferroelectric capacitor has a construction in which even whenthe electric field (applied voltage) is zero, a remaining polarizationof a polarity in accordance with the hysteresis of voltage applicationremains in the ferroelectric layer, and in the ferroelectric memorydevice non-volatility of the storage data is realized by representingstorage data by the remaining polarization of the ferroelectriccapacitor.

In a non-volatile memory device using such ferroelectric capacitors, itis an important objective to reduce variations in the hysteresischaracteristics of the ferroelectric capacitors and reduce changes inthe hysteresis characteristic accompanying the use.

More specifically, FIGS. 14 to 16 are diagrams for explaining aconventional ferroelectric memory device, FIG. 14 is a plan viewillustrating a memory cell array in the ferroelectric memory device,FIG. 15 is a cross-sectional view along a line XV--XV portion in FIG.14, and FIG. 16 is a plan view illustrating a position relation betweenupper electrodes and a lower electrode of ferroelectric capacitors.

In the figures, reference numeral 200 designates a memory cell arrayconstituting a ferroelectric memory device, a plurality of transistorregions 220a are arranged on a silicon substrate 201 in a firstdirection D1, and an insulating film 202 for element isolation is formedon a portion of the silicon substrate 201, except the transistor regions220a.

On both sides of the transistor regions 220a in a line along the firstdirection D1, lower electrodes (first electrodes) 211 are formed as cellplate electrodes on the insulating film 202 for element isolation viafirst interlayer insulating films 203. The lower electrode 211 comprisesa metallic material, such as titanium and platinum, and has astripe-shaped plan configuration extending along the first direction D1.On surfaces of the lower electrodes 211, ferroelectric layers 213 areformed.

On the ferroelectric layers 213 on the surfaces of the lower electrodes211, upper electrodes (second electrodes) 212 comprising a metallicmaterial, such as titanium and platinum, are formed corresponding to therespective transistor regions 220a. That is, on the ferroelectric layers213, the plurality of upper electrodes 212 are arranged along the firstdirection D1. A plan shape of each upper electrode 212 is a rectangularshape having the first direction D1 as its longitudinal direction, andas is known from FIG. 14, the area of each upper electrode 212 issmaller than that of the lower electrode 211. Here, ferroelectriccapacitors 210 are constituted by the lower electrode 211, the upperelectrodes 212, and the ferroelectric layer 213 located between theseelectrodes, and the surfaces of the ferroelectric layers 213 and thesurfaces of the upper electrodes 211 are covered with second interlayerinsulating films 204.

In this case, the upper electrode 212 is disposed in a center portion ofthe lower electrode 211, and the distance O₁₁ (hereinafter referred toas non-overlap width) between a side 211a₁ of the lower electrode 211and a side 211a₁ of the upper electrode 211 opposite thereto is madeequal to the distance O₁₂ (hereinafter referred to as non-overlap width)between the other side 211a₂ of the lower electrode 211 and a side 211a₂of the upper electrode 211 opposite thereto.

Between the pair of lower electrodes 211 that sandwich the transistorregions 220a opposing to each other, a pair of word lines (secondwirings) 223a and 223b comprising polysilicon are disposed so as tostraddle over the plurality of transistor regions 220a arranged in aline. A source diffusion region 222 and drain diffusion regions 221 of amemory transistor 220 constituting a memory cell are formed on bothsides of the word lines 223a and 223b in each transistor region 220a.Portions of the word lines 223a and 223b located above each transistorregion 220a constitute gate electrodes of the memory transistor 220, andare located on the substrate surface via gate insulating films 202a. Thesurfaces of the diffusion regions 221 and 222 and the word lines 223aand 223b are covered with the first and second interlayer insulatingfilms 203 and 204. In FIG. 14, these interlayer insulating films are notshown.

The source diffusion region 222 located between the pair of word lines223a and 223b in each transistor region 220a is connected to a bit line233b extending along a second direction D2 perpendicular to the firstdirection D1, through a contact hole 205b formed in the first and secondinterlayer insulating films 203 and 204. The drain diffusion regions 221located outside the opposite word lines 223a and 223b in each transistorregion 220a are electrically connected to the upper electrodes 212 byconnecting wirings 233a. That is, one end of the connecting wiring 233ais connected to the upper electrode 212 through a contact hole 204aformed in the second interlayer insulating film 204, and the other endof the connecting wiring 233a is connected to the drain diffusion region221 through a contact hole 205a formed in the first and secondinterlayer insulating films 203 and 204.

The lower electrodes 211 and the ferroelectric layers 213 are formed bysuccessively forming films of a metallic material, such as titanium andplatinum, and a ferroelectric material on the interlayer insulating film203 and patterning these films, and the upper electrodes 212 are formedby forming a film of a metallic material, such as titanium and platinum,on the ferroelectric layer 213 and patterning the film. The bit lines233b and the connecting wirings 233a are formed by patterning a metallicfilm, such as aluminum, formed on the interlayer insulating film 204.The word lines 223a and 223b are formed by patterning a polysilicon filmthat is formed on the gate insulating films 202a and the insulating film202 for element isolation.

The first interlayer insulating film 203 comprises an insulatingmaterial, such as NSG (oxide silicon based) and BPSG (boron, phosphinedoped oxide silicon), and the second interlayer insulating film 204comprises, for example, PSG (phosphine doped oxide silicon).

As the ferroelectric material composing the ferroelectric layer 213 ofthe ferroelectric capacitors, KNO₃, PbLa₂ O₃ -ZrO₂ -TiO₂, PbTiO₃ -PbZrO₃or the like has been known. In addition, PCT International PublicationWO 93/12542 discloses a ferroelectric material that has extremely lowfatigueness as compared with PbTiO₃ -PbZrO₃, being suitable for aferroelectric memory device.

The operation will be described briefly.

In the ferroelectric memory device with the construction as describedabove, when, for example, the word line 223a is selected andsubsequently, one of the lower electrodes 211 (for example, theuppermost lower electrode shown in FIG. 14) is driven, thereby makingthe voltage level thereof the level corresponding to the logical voltage"H", storage data of the ferroelectric capacitors 210 formed on thislower electrode are read out onto the respective bit lines 233b throughthe connecting wirings 233a and the transistors 220.

A brief description is given of the principle of this reading outoperation. FIG. 17 is a graph showing the hysteresis characteristic ofthe ferroelectric capacitor, in which the ordinate represents thepolarization charge amount P of the ferroelectric capacitor and theabscissa represents the electric field E applied to the ferroelectriccapacitor. P₁ and P₂ show the polarization charge amounts that aregenerated when the electric fields E₁ and E₂ (=-E₁) are applied to theferroelectric capacitor, respectively, P_(r1) shows the residual chargeamount against the applied voltage E₁, P_(r2) shows the residual chargeamount against the applied voltage E₂ (=-E₁), E_(c1) shows the counterelectric field against the residual charge amount P_(r2), and E_(c2)shows the counter electric field against the residual charge amountP_(r1). In this ferroelectric memory device, the reading out voltagethat is applied to the ferroelectric capacitor at reading out of data(that is, the voltage applied to the lower electrode) is set to avoltage that makes the electric field applied to the ferroelectriccapacitor, E₂.

In the ferroelectric memory device, predetermined storage data arewritten into the respective memory cells, and the residual charge amountof the ferroelectric capacitor constituting the memory cell correspondsto the residual charge amount P_(r1) or P_(r2) corresponding to thestorage data "1" or "0", respectively. In this state, when apredetermined word line is driven and the reading out voltage is appliedto a predetermined lower electrode of ferroelectric capacitors, theelectric charge corresponding to the residual charge amount P_(r1) orP_(r2) is read out from each ferroelectric capacitor that is positionedon the predetermined lower electrode onto the bit line.

For example, the difference ΔP₂ (=P_(r2-P) ₂) between the polarizationcharge amount P₂ corresponding to the applied voltage E₂ and theresidual charge amount P_(r2) is read out from the ferroelectriccapacitor having the residual charge amount P_(r2) as signal chargescorresponding to the storage data onto the bit line 233b. Further, thedifference ΔP₁ (=P_(r1) -P₂) between the polarization charge amount P₂corresponding to the applied voltage E₂ and the residual charge amountP_(r1) is read out from the ferroelectric capacitor having the residualcharge amount P_(r1) as signal charges corresponding to the storage dataonto the bit line. In this case, since the charge amount (P_(r1) -P₂)and the charge amount (P_(r2) -P₂) that are read out onto the bit linesare different from each other, it is possible to discriminate the datathat are stored in the memory cells due to the difference in the chargeamount. In addition, in the construction in which the data are read outfrom the ferroelectric capacitors as described above, as for the memorycell in which the residual charge amount of the ferroelectric capacitoris the residual charge amount P_(r1), data destruction occurs by thereading out operation. For this reason, the ferroelectric memory devicehas a circuit construction in which after reading out of data, thestorage data before reading out is written into each ferroelectriccapacitor to modify the data of the memory cell.

Then, the signal charges corresponding to the storage data that are readout onto the respective bit lines 233b are amplified by sense amplifiers(not shown) to be output to the outside of the ferroelectric memorydevice. Thereafter, the voltage level of the lower electrode 211 is madea level corresponding to the logical voltage "L" to make the word line223a the unselected state, thereby completing the reading out.

In the conventional ferroelectric capacitors 210, however, variations inthe characteristics, i.e., variations in polarizability of theferroelectric layers, are large, and changes in the characteristic,i.e., changes in polarizability with passage of time are likely tooccur.

More specifically, the initial values of the polarization charge amountsP₁ and P₂, the counter electric fields E_(c1) and E_(c2), or theresidual charge amounts P_(r1) and P_(r2) against the applied fields E₁and E₂ in the hysteresis characteristic curves of the ferroelectriccapacitor shown in FIG. 17 widely vary between the memory cells in onedevice (ferroelectric memory device) or between the devices, and changesin the hysteresis characteristic with passage of time (change fromnormal characteristic shown by curves La to deteriorated characteristicshown by curves Lb) are likely to occur in a short time.

The present invention is directed to solving the above-describedproblems, and has an object to provide a semiconductor device with largelongevity and a good fabrication yield, in which variations incharacteristics of ferroelectric capacitors can be suppressed andcharacteristic changes with passage of time can be reduced.

DISCLOSURE OF THE INVENTION

A semiconductor device according to the present invention includes afirst electrode extending along a first direction and having a planconfiguration having a second direction perpendicular to the firstdirection as its width direction; second electrodes disposed opposite tothe first electrode and having a plan configuration of the size in thefirst direction and the size in the second direction being equal to eachother, or a plan configuration of the size in the first direction beingshorter than the size in the second direction; and a ferroelectric layerdisposed between the first electrode and the second electrodes; thefirst and second electrodes and the ferroelectric layer between the bothelectrodes constituting ferroelectric capacitors.

Preferably, wherein the second electrodes are formed by patterning apredetermined conductive material layer, the plurality of secondelectrodes are arranged along the first direction, and the arrangementintervals between the adjacent second electrodes are set to be theminimum size of an opening pattern that can be formed on the conductivematerial layer.

More preferably, wherein a plan configuration of the second electrode isa polygonal configuration, and all the sizes of respective angles in theplan configuration of the second electrode are larger than 90°.

In another embodiment, the device includes first electrodes extendingalong a first direction and having a plan configuration having a seconddirection perpendicular to the first direction as its width direction; aplurality of second electrodes positioned opposite to the firstelectrodes and arranged in the form of a matrix along the firstdirection and the second direction; and ferroelectric layers disposedbetween the first electrodes and the second electrodes; the firstelectrodes, the ferroelectric layers, and the plurality of secondelectrodes constituting a plurality of ferroelectric capacitors.

Preferably, the second electrodes have a plan configuration of the sizein the first direction and the size in the second direction being equalto each other, or a plan configuration of the size in the firstdirection being shorter than the size in the second direction.

In another embodiment, the device includes a first electrode extendingalong a first direction and having a plan configuration having a seconddirection perpendicular to the first direction as its width direction;second electrodes disposed opposite to the first electrode and having aplan configuration having a direction between the first direction andthe second direction as its longitudinal direction; and a ferroelectriclayer disposed between the first electrode and the second electrodes;the first and second electrodes and the ferroelectric layer between theboth electrodes constituting ferroelectric capacitors.

Preferably, wherein a plan configuration of the second electrode is apolygonal configuration, and all the sizes of respective interior anglesin the plan configuration of the second electrode are larger than 90°.

In another embodiment, the device includes a first electrode extendingalong a first direction and having a plan configuration having a seconddirection perpendicular to the first direction as its width direction;second electrodes disposed opposite to the first electrode and having afirst side that is closest and opposite to a first side of the firstelectrode parallel to the first direction, and a second side that isclosest and opposite to a second side of the first electrode parallel tothe first direction; and a ferroelectric layer disposed between thefirst electrode and the second electrodes; the first and secondelectrodes and the ferroelectric layer between the both electrodesconstituting ferroelectric capacitors; and the length of the first sideof the second electrode being larger than the length of the second sidethereof, and the distance between the first side of the second electrodeand the first side of the first electrode being longer than the distancebetween the second side of the second electrode and the second side ofthe first electrode.

Preferably, a plan configuration of the second electrode is a polygonalconfiguration, and all the sizes of respective interior angles in theplan configuration of the second electrode are larger than 90°.

In another embodiment, the device constitutes a ferroelectric memorydevice with a plurality of memory cells respectively comprisingferroelectric capacitors and memory transistors and arranged in the formof a matrix, cell plate lines for driving the ferroelectric capacitors,a plurality of bit lines corresponding to respective memory cellcolumns, a plurality of word lines corresponding to respective memorycell rows, for selecting the memory transistors, and sense amplifiersconnected to the respective bit lines and amplifying data signals on thepredetermined bit lines. This ferroelectric memory device includes firstelectrodes extending along a first direction, having a planconfiguration having a second direction perpendicular to the firstdirection as its width direction, and connected to the cell plate lines;second electrodes disposed opposite to the first electrodes and having aplan configuration of the size in the first direction and the size inthe second direction being equal to each other, or a plan configurationof the size in the first direction being shorter than the size in thesecond direction; and ferroelectric layers disposed between the firstelectrodes and the second electrodes; the first and second electrodesand the ferroelectric layers constituting the ferroelectric capacitors.

Preferably, the device includes a first electrode constituting theferroelectric capacitors extending along a first direction and having aplan configuration having a second direction perpendicular to the firstdirection as its width direction; second electrodes constituting theferroelectric capacitors disposed opposite to the first electrode; aferroelectric layer constituting the ferroelectric capacitors disposedbetween the first electrode and the second electrodes; an insulatingfilm formed to cover the surfaces of the second electrodes and havingcontact holes formed on positions of the surfaces of the secondelectrodes that are shifted from the center positions to one side of thefirst electrode along the first direction; and wirings formed on theinsulating film and connected to the second electrodes through thecontact holes.

Alternatively, the device includes a first electrode constituting theferroelectric capacitors extending along a first direction and having aplan configuration having a second direction perpendicular to the firstdirection as its width direction; second electrodes constituting theferroelectric capacitors disposed opposite to the first electrode; aferroelectric layer constituting the ferroelectric capacitors disposedbetween the first electrode and the second electrodes; an insulatingfilm formed to cover the surfaces of the second electrodes and havingcontact holes formed on predetermined positions of the surfaces of thesecond electrodes; and wirings formed on the insulating film andelectrically connected to the second electrodes; the second electrodeshaving a structure in which the whole is divided into plural electrodeportions by forming notches at predetermined sides; and the wiringsbeing connected to parts of the plural electrode portions constitutingthe second electrodes through the contact holes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view illustrating a memory cell array of aferroelectric memory device in accordance with a first embodiment of thepresent invention.

FIG. 2 is a cross-sectional view along a line II--II portion in FIG. 1.

FIG. 3 is a plan view illustrating a position relation between a lowerelectrode and upper electrodes constituting ferroelectric capacitorsaccording to the first embodiment of the invention.

FIG. 4 is a plan view illustrating a memory cell array of aferroelectric memory device in accordance with a second embodiment ofthe present invention.

FIG. 5 is a plan view illustrating a position relation between a lowerelectrode and upper electrodes constituting ferroelectric capacitorsaccording to the second embodiment of the invention.

FIG. 6 is a plan view illustrating a memory cell array of aferroelectric memory device in accordance with a third embodiment of thepresent invention.

FIG. 7 is a plan view illustrating a position relation between a lowerelectrode and upper electrodes constituting ferroelectric capacitorsaccording to the third embodiment of the invention.

FIG. 8 is a plan view for explaining a ferroelectric memory device inaccordance with a fourth embodiment of the present invention, and showsa position relation between a lower electrode and upper electrodes offerroelectric capacitors constituting the ferroelectric memory device.

FIG. 9 is a plan view for explaining a ferroelectric memory device inaccordance with a fifth embodiment of the present invention, and shows aposition relation between a lower electrode and upper electrodes offerroelectric capacitors constituting the ferroelectric memory device.

FIGS. 10(a)-10(c) are plan views for explaining a ferroelectric memorydevice in accordance with a sixth embodiment of the present invention,where FIG. 10(a) is a diagram illustrating a position relation between alower electrode and upper electrodes of ferroelectric capacitorsconstituting the ferroelectric memory device, FIG. 10(b) is a diagramfor explaining a configuration of the upper electrode according to thesixth embodiment of the invention, and FIG. 10(c) is a diagramillustrating the configuration of the upper electrode according to thesixth embodiment of the invention.

FIG. 11 is a plan view illustrating a construction of a memory cellarray using the structure of the upper electrode of the ferroelectriccapacitor according to the sixth embodiment and effectively utilizingthe device area.

FIG. 12 is a plan view illustrating a memory cell array of aferroelectric memory device in accordance with a seventh embodiment ofthe present invention.

FIG. 13 is a plan view illustrating a position relation between a lowerelectrode and upper electrodes constituting ferroelectric capacitorsaccording to the seventh embodiment of the invention.

FIG. 14 is a plan view illustrating a memory cell array of aconventional ferroelectric memory device.

FIG. 15 is a cross-sectional view along a line XV--XV portion in FIG.14.

FIG. 16 is a plan view illustrating a position relation between a lowerelectrode and upper electrodes of ferroelectric capacitors in theconventional ferroelectric memory device.

FIG. 17 is a graph showing the hysteresis characteristic of theferroelectric capacitor.

BEST EMBODIMENTS FOR CARRYING OUT THE INVENTION

Initially, a description is given of the aiming point and fundamentalprinciple of the present invention.

As a result of earnest study to achieve the above-described object, theinventors of the present invention found that the variations incharacteristics and the characteristic changes of ferroelectriccapacitors were based on deterioration of material quality of theferroelectric layers due to various processes after the ferroelectriclayers constituting the ferroelectric capacitors are formed.

In other words, since the lower electrodes and the ferroelectric layersare formed by forming a metallic film such as platinum and aferroelectric film on the interlayer insulating film and patterningthese films, when the patterning is performed, etchant or the likeintrudes from the side surfaces of the ferroelectric layer that areexposed by etching processing as impurities, thereby causing materialquality deterioration at the side portions of the ferroelectric layer.In addition, since the interface between the ferroelectric layer and thelower electrode is exposed at the etching, a resistance layer or thelike is formed at the interface portion by intrusion of impurities.

Further, since the upper electrodes are formed by patterning a metallicfilm such as platinum formed on the ferroelectric layer, when thepatterning is performed, portions of the ferroelectric layer exposed byremoval of the metallic film are subjected to etching processing,thereby causing material quality deterioration of the ferroelectriclayer at the periphery of the upper electrodes.

Furthermore, when the contact holes are formed by selectively removingportions of the interlayer insulating film on the upper electrodes,impurities intrude into the ferroelectric layer through the upperelectrodes exposed in the contact holes, and further when the connectingwirings are formed, titanium or the like serving as a constitutionalmaterial of the connecting wirings intrudes into the ferroelectric layerthrough the upper electrodes. Thereby, material quality deteriorationoccurs at portions of the ferroelectric layer corresponding to thecontact holes.

From these facts, the width size of the lower electrode in a directionperpendicular to a longitudinal direction is widened and the upperelectrodes are arranged as distantly as possible from the side portionsof the lower electrode, as well as the areas of the upper electrodes areincreased, whereby the influences by the portions deteriorated due toimpurity diffusion, of the ferroelectric layer in the ferroelectriccapacitors can be reduced, while when the sizes of the lower electrodeand the upper electrodes are simply increased, for example, thenon-overlap widths O₁₁ and O₁₂ shown in FIG. 16 are made larger than thewidth W₂ of the upper electrode 212, the width W₁ of the lower electrode211 becomes larger than (W₂ +O₁₁ +O₁₂), so that the layout area on thesubstrate of the memory cell array is eminently increased, resulting ina new problem.

Therefore, the inventors of the present invention further found therelevancy between the configurations of the upper electrodesconstituting the ferroelectric capacitors and such as the characteristicvariations, and the relevancy between the positions of the contact holeson the upper electrodes and such as the characteristic variations, anddeveloped a device that can avoid the occurrence of the above-describednew problem on the basis of these.

More specifically, the inventors of the present invention noticed thatbecause the length L₂ of the upper electrode 212 was larger than itswidth W₂ in the conventional ferroelectric capacitor 210, theferroelectric capacitors were greatly affected by the portions havingthe material quality deterioration at the sides of the ferroelectriclayer, thereby making it likely to cause the characteristic variationsand characteristic changes of the ferroelectric capacitors, and foundthat the portions causing the material quality deterioration, of theferroelectric layer constituting the ferroelectric capacitors weremainly portions that are positioned in the vicinity of the sides of thelower electrode, and by making the plan configurations of the upperelectrodes the configurations having the width direction of the lowerelectrode as its longitudinal direction, the portions having thematerial quality deterioration, of the ferroelectric layer, included inthe ferroelectric capacitors could be reduced without reducing the areasof the upper electrodes.

Further, they found by arranging the contact holes of the upperelectrodes at positions shifted from the center positions of the upperelectrodes toward the side of the lower electrode, diffusion ofimpurities from the contact holes to the ferroelectric layer through theupper electrodes can be suppressed.

A description is given of respective embodiments of the presentinvention on the basis of such aiming point and fundamental principle.

Embodiment 1

FIGS. 1 to 3 are diagrams for explaining a ferroelectric memory deviceaccording to a first embodiment of the present invention, FIG. 1 is aplan view illustrating a part of a memory cell array constituting theferroelectric memory device, FIG. 2 is a cross-sectional view along aline II--II portion in FIG. 1, and FIG. 3 is a plan view illustrating aposition relation between upper electrodes and a lower electrode offerroelectric capacitors constituting memory cells.

In the figures, reference numeral 100a designates a memory cell arrayconstituting a ferroelectric memory device, transistor regions 120a arearranged on a silicon substrate 101 in the form of a matrix along afirst direction D1 and a second direction D2 perpendicular to the firstdirection, and an insulating film 102 for element isolation is formed ona surface region of the silicon substrate 101, except the transistorregions.

On both sides of the transistor regions 120a of each line along thefirst direction D1, lower electrodes (first electrodes) 111a aredisposed as cell plate electrodes. The lower electrodes 111a are formedby patterning a metallic film, such as titanium and platinum, anddisposed on the insulating film 102 for element isolation via interlayerinsulating films 103. Further, the lower electrodes 111a extend alongthe first direction D1, and have stripe-shaped plans having the seconddirection perpendicular to the first direction as its wiring widthdirection, and ferroelectric layers 113 are formed on surfaces of thelower electrodes.

On the ferroelectric layers 113 on the surfaces of the respective lowerelectrodes 111a, upper electrodes (second electrodes) 112a are formed bypatterning a metallic film, such as platinum. That is, on theferroelectric layers 113 on the respective lower electrodes 111a, theplurality of upper electrodes 112a are arranged along the firstdirection D1. A plan shape of each upper electrode 112a is a rectangularshape having the second direction D2 as its longitudinal direction, andthe area of each upper electrode 112a is smaller than that of the lowerelectrode 111a. The surfaces of the ferroelectric layers 113 and thesurfaces of the upper electrodes 112a are covered with second interlayerinsulating films 104. In FIG. 1, the ferroelectric layers 113 and thefirst and second interlayer insulating films 103 and 104 are not shown.

At this time, the lower electrode 111a, the upper electrodes 112a thatare located above the lower electrode, and the ferroelectric layer 113between the lower electrode and the upper electrodes constituteferroelectric capacitors 110a. The ferroelectric capacitors 110a aredisposed on both sides of the transistor regions 120a.

Between both of the lower electrodes 111a that sandwich the transistorregions 120a opposing to each other, a pair of word lines 123a₁ and123a₂ comprising polysilicon is disposed so as to straddle over theplurality of transistor regions 120a arranged in a line. In this case,the word lines 123a₁ and 123a₂ have zigzag-shaped plans so that they donot overlap with positions where contact holes 105a and 105b are formedin the transistor regions 120a. A source diffusion region 122 and draindiffusion regions 121 of a transistor constituting a memory cell areformed on both sides of the word lines in each transistor region.Portions of the word lines located above each transistor regionconstitute gates of the transistor, and are located on the surfaceregion of the substrate 101 via gate insulating films 102a. The surfacesof the diffusion regions 121 and 122 and the word lines 123a₁ and 123a₂are covered with the first and second interlayer insulating films 103and 104.

The source diffusion region 122 located inside the pair of word lines ateach transistor region 120a is connected to a bit line 113b extendingalong the second direction perpendicular to the first direction D1,through a contact hole 105b that is formed in the first and secondinterlayer insulating films 103 and 104. The drain diffusion regions 121located outside the pair of word lines at each transistor region 120aare electrically connected to the upper electrodes 112a of theferroelectric capacitors 110a corresponding to each transistor region120a by connecting wirings 113a. That is, one end of the connectingwiring 113a is connected to the upper electrode 112a through a contacthole 104a that is formed in the second interlayer insulating film 104,and the other end of the connecting wiring 113a is connected to thedrain diffusion region 121 through a contact hole 105a that is formed inthe first and second interlayer insulating films 103 and 104.

In this case, the first interlayer insulating film 103 comprises aninsulating material, such as NSG (oxide silicon based) and BPSG (boron,phosphine doped oxide silicon), and the second interlayer insulatingfilm 104 comprises an insulating material, for example, PSG (phosphinedoped oxide silicon).

As a ferroelectric material of the ferroelectric layer 113 of theferroelectric capacitors 110a, KNO₃, PbLa₂ O₃ -ZrO₂ -TiO₂, PCTiO₃-PbZrO₃ or the like has been known. In addition, PCT InternationalPublication WO 93/12542 discloses a ferroelectric material that hasextremely low fatigueness as compared with PbTiO₃ -PbZrO₃, beingsuitable for a ferroelectric memory device.

The connecting wirings 113a and the bit lines 113b are formed bypatterning a titanium layer and an aluminum layer that are successivelyformed on the substrate. In addition, the connecting wirings 113a andthe bit lines 113b may be have a single-layer structure comprising analuminum layer. In this case, they may be formed by patterning theidentical aluminum layer, or may be formed by patterning differentaluminum layers.

In the first embodiment of the invention, especially as shown in FIG. 3,the plan configuration of the upper electrode 112a is made a planconfiguration of the size L₂ in the first direction D1 being smallerthan the size W₂ in the second direction D2. The area of the upperelectrode 112a that is disposed opposite to the lower electrode 111a issmaller than the area of the lower electrode 111a. In this case, thedistance O₁₁ (hereinafter referred to as first non-overlap width)between a first side 111a₁ of the lower electrode 111a and a first side112a₁ of the upper electrode 112a opposite thereto is made equal to thedistance O₁₂ (hereinafter referred to as second non-overlap width)between a first side 111a₂ of the lower electrode 111a and a first side112a₂ of the upper electrode 112a opposite thereto, and these first andsecond non-overlap widths O₁₁ and O₁₂ are set to be smaller than thesize W₂ of the upper electrode 112a in the second direction D2 (widthdirection of the lower electrode).

A function and effects will be described.

The data reading out operation in the ferroelectric memory deviceaccording to the first embodiment is identical as the operation in theconventional ferroelectric memory device.

In the first embodiment of the invention, in the ferroelectric memorydevice, since the plurality of upper electrodes 112a are arranged on thelower electrode (cell plate electrode) llla having a stripe-shaped planconfiguration via the ferroelectric layer 113, along a longitudinaldirection of the lower electrode 111a, thereby constituting theplurality of ferroelectric capacitors 110a, and the size L₂ of the upperelectrode 112a in the longitudinal direction of the lower electrode issmaller than the size W₂ in the direction perpendicular to the size L₂,regions of the upper electrodes 112a that are piled up to side portionsof the ferroelectric layer 113 at which material quality deteriorationis caused can be reduced without reducing the areas of the upperelectrodes 112a. Consequently, variations in characteristics as thewhole of the ferroelectric capacitors are reduced, and characteristicchanges with passage of time are moderated.

In this case, since the width L₂ of the region of the upper electrode112a that is affected by the material quality deterioration of theferroelectric layer is small, even when the non-overlap widths O₁₁ andO₁₂ are made smaller, the variations in characteristics as the whole ofthe ferroelectric capacitors and the characteristic changes can besuppressed, whereby the width W₁ (=W₂ +O₁₁ +O₁₂) of the lower electrode111a can be made smaller, thereby reducing the layout area of the memorycell array.

Further, in the first embodiment, since the contact holes 104a formed onthe upper electrodes 112a are arranged at positions of the upperelectrodes 112a that are shifted from the center positions to one side,the material quality deterioration of the ferroelectric layer 113 due tothe impurity diffusion from the contact holes can be prevented fromspreading over portions corresponding to the center of the upperelectrodes 112a.

More specifically, when the contact holes 104a are formed and theconnecting wirings 113a are formed, impurities intrude into theferroelectric layer 113 through the upper electrodes 112a that areexposed in the contact holes 104a, thereby deteriorating the material ofthe ferroelectric layer 113. This material quality deterioration causesvariations in characteristics of the ferroelectric capacitors andcharacteristic deterioration, and if the material quality deteriorationis caused at portions corresponding to the center of the upperelectrodes 112a, it combines with the deterioration that is caused atthe sides of the lower electrode 111a, so that the material qualitydeterioration of the ferroelectric layer spreads over an extremely widerange of the ferroelectric layer.

Meanwhile, as in the first embodiment of the invention, in theferroelectric capacitors in which the contact holes 104a formed on theupper electrodes 112a are arranged at positions of the upper electrodes112a that are shifted from the center positions to one side, regions ofthe ferroelectric layer 113 at which the material quality deteriorationis caused by diffusion of impurities from the contact holes 104a canoverlap with regions at the sides of the lower electrode 111a at whichthe material quality deterioration is caused, thereby keeping wideregions of the ferroelectric layer 113 at which no deterioration ofmaterial quality is caused. Consequently, variations in characteristicsas the ferroelectric capacitors and characteristic deterioration can beeffectively suppressed.

In addition, in the first embodiment, although there is described thecase in which the width W₂ of the upper electrode 112a (size in thesecond direction D2) is smaller than its length L₂ (size in the firstdirection D1), the width W₂ and the length L₂ of the upper electrode112a may be the identical size. Also in this case, it is possible tosuppress the variations in characteristics as the whole of theferroelectric capacitors and the characteristic changes.

Embodiment 2

FIGS. 4 and 5 are diagrams for explaining a ferroelectric memory deviceaccording to a second embodiment of the present invention, FIG. 4 is aplan view illustrating a memory cell array constituting theferroelectric memory device, and FIG. 5 is a plan view illustrating aposition relation between upper electrodes and a lower electrodeconstituting ferroelectric capacitors in the memory cell array.

In a memory cell array of a ferroelectric memory device according to thesecond embodiment, the arrangement intervals between the adjacent upperelectrodes in the first embodiment are set to be the minimum size(minimum process size) S_(2b) of an opening pattern that can be formedon a conductive material layer constituting the upper electrodes, andthe arrangement of the respective contact holes at the transistorregions in the first embodiment is changed according to this minimumsize.

More specifically, in FIGS. 4 and 5, the same reference numerals asthose shown in FIGS. 1 to 3 designate the same parts as in the firstembodiment, and numeral 100b designates a memory cell array constitutinga ferroelectric memory device. In this memory cell array 100b,transistor regions 120b are arranged on the silicon substrate 101 in theform of a matrix along a first direction D1 and a second direction D2perpendicular to the first direction, and the insulating film 102 forelement isolation is formed on a surface region of the silicon substrate101, except the transistor regions. On both sides of the transistorregions 120b of each line along the first direction D1, the lowerelectrodes (first electrodes) 111a on which the ferroelectric layers 113are formed as in the first embodiment are disposed as cell plateelectrodes.

On the ferroelectric layers 113 on the surfaces of the respective lowerelectrodes 111a, a plurality of upper electrodes (second electrodes)112b that are formed by patterning a metallic film, such as platinum,are arranged along the first direction D1. At this time, the arrangementintervals of the adjacent upper electrodes 112b are set to be theminimum process size S_(2b). A plan shape of each upper electrode 112bis a rectangular shape having the second direction D2 as itslongitudinal direction as in the first embodiment, and the area of eachupper electrode 112b is smaller than that of the lower electrode 111a.At this time, the lower electrode 111a, the plurality of upperelectrodes 112b that are located above the lower electrode, and theferroelectric layer 113 between the lower electrode and the upperelectrodes constitute a plurality of ferroelectric capacitors 110b. Theferroelectric capacitors 110b are disposed on both sides of thetransistor regions 120b.

Between both of the lower electrodes 111a that sandwich the transistorregions 110b opposing to each other, a pair of word lines 123b₁ and123b₂ comprising polysilicon is disposed so as to straddle over theplurality of transistor regions 120b arranged in a line. In this case,plan configurations of the word lines 123b₁ and 123b₂ are straightshapes. As in the first embodiment, a source diffusion region and draindiffusion regions of a transistor constituting a memory cell are formedon both sides of the word lines in each transistor region. Portions ofthe word lines located above each transistor region constitute gateelectrodes of the transistor, and are located on the surface region ofthe substrate 101 via gate insulating films. The surfaces of thediffusion regions and the word lines are covered with the first andsecond interlayer insulating films as in the first embodiment (notshown).

The source diffusion region located inside the pair of word lines ateach transistor region 120b is connected to a connecting wiring 113c inthe contact hole 105b that is formed in the first and second interlayerinsulating films, and the connecting wiring 113c is connected to a bitline 115 extending along the second direction perpendicular to the firstdirection D1, through a contact hole 105c that is formed in a thirdinterlayer insulating film on the connecting wiring (not shown). Thedrain diffusion regions located outside the pair of word lines at eachtransistor region 120b are electrically connected to the upperelectrodes 112b of the ferroelectric capacitors corresponding to eachtransistor region by the connecting wirings 113a. That is, one end ofthe connecting wiring 113a is connected to the upper electrode 112bthrough the contact hole 104a that is formed in the second interlayerinsulating film, and the other end of the connecting wiring 113a isconnected to the drain diffusion region through the contact hole 105athat is formed in the first and second interlayer insulating films.

In this case, by making the arrangement intervals between the upperelectrodes 112b narrower than those in the first embodiment, the contactholes 105a on the drain diffusion regions 121 (refer to FIG. 2) and thecontact hole 105b on the source diffusion region 122 (refer to FIG. 2)in each transistor region 120b are arranged on a straight line parallelto the second direction D2. The connecting wirings 113a and 113c have adouble-layer structure comprising titanium and aluminum as in the firstembodiment. The bit lines 115 are formed by patterning an aluminum layeror the like that is formed on the conductive layer of the double-layerstructure.

The other constructions are identical as in the first embodiment, thefirst and second interlayer insulating films comprise the identicalmaterial as in the first embodiment, and the ferroelectric layers 113 ofthe ferroelectric capacitors comprise the same ferroelectric material asin the first embodiment.

In the second embodiment with the construction as described above, sincethe arrangement intervals between the plurality of upper electrodes 112bthat are arranged in a line on the lower electrode 111a are set to bethe minimum process size, the layout area that is occupied by the memorycell array can be reduced to about 60% of the layout area according tothe first embodiment, in addition to the effects of the firstembodiment.

Embodiment 3

FIGS. 6 and 7 are diagrams for explaining a ferroelectric memory deviceaccording to a third embodiment of the present invention, FIG. 6 is aplan view illustrating a memory cell array constituting theferroelectric memory device, and FIG. 7 is a plan view illustrating aposition relation between upper electrodes and a lower electrodeconstituting ferroelectric capacitors in the memory cell array.

In the figures, reference numeral 100c designates a memory cell array ofa ferroelectric memory device according to the third embodiment, and thesame reference numerals as those shown in FIGS. 1 to 3 designate thesame parts as in the first embodiment.

This memory cell array 100c has lower electrodes 111c with widths W₂(size in the second direction D2) that are increased as compared withthose of the lower electrodes 111a, in place of the lower electrodes111a according to the first embodiment, and the upper electrodes 112aare arranged in two lines along the first direction D1 on the lowerelectrodes 111c.

In this case, the arrangement intervals between the upper electrodes112a that are arranged on the lower wiring 111c along the firstdirection D1 are set to be the same size S₂ as in the first embodiment,and the arrangement interval between the upper electrodes 112a that arearranged along the second direction is set to be the minimum processsize S_(22c). The other constructions are identical as in the memorycell array 100a of the first embodiment.

In the third embodiment with the construction as described above, sincea plan shape of the upper electrode 112a that is disposed on the lowerelectrode 111c is made a shape of the size L₂ in a length directionbeing smaller than the size W₂ in a width direction, the width L₂ of aregion of the upper electrode 112a that is affected by deterioration ofmaterial quality of the ferroelectric layer becomes small, whereby evenwhen the distances O₁₁ and O₁₂ (non-overlap widths) between the sides ofthe lower electrode and the adjacent sides of the upper electrode aremade smaller, variations in characteristics as the whole of theferroelectric capacitors and characteristic changes can be suppressed.

Further, since the lower electrode 111c has a wide structure, and theupper electrodes 112a are arranged in two lines along the firstdirection D1 on the lower electrode 111c, the area of the lowerelectrode corresponding to two lines of the upper electrodes 112a can bereduced as compared with the area according to the first embodiment,resulting in a high-density layout on the substrate of the memory cellarray.

Furthermore, in this embodiment of the invention, since the arrangementinterval between the upper electrodes 112a that are arranged along thewidth direction on the lower electrode 111c is set to be the minimumprocess size S_(22c), as a result, the area that is occupied on thesubstrate of the memory cell array can be reduced by about 10% of thearea according to the first embodiment.

Embodiment 4

FIG. 8 is a diagram for explaining a ferroelectric memory deviceaccording to a fourth embodiment of the present invention, and shows aplan configuration of upper electrodes of ferroelectric capacitorsconstituting the ferroelectric memory device.

In the figure, reference numeral 112d designates an upper electrodeconstituting a ferroelectric capacitor according to the fourthembodiment, and the plurality of upper electrodes 112d are arranged atpredetermined intervals on the lower electrode 111a along the seconddirection D2, as in the first embodiment. In this case, the upperelectrode 112d has a plan shape that is obtained by chamfering fourcorners of the upper electrode 112a of a rectangular shape in the firstembodiment. That is, the upper electrode 112d has an octagonal shapehaving the second direction D2 as its longitudinal direction, and all ofinterior angles are larger than 90°. The other constructions areidentical as in the first embodiment.

In the fourth embodiment with such a construction, since the upperelectrodes 112d have polygonal shapes in which all of the interiorangles are larger than 90°, when the upper electrodes 112d arepatterned, variations in the shapes at the upper electrode angle partscan be reduced, whereby occurrence of variations in characteristics ofthe ferroelectric capacitors and characteristic changes can be furthersuppressed as compared with the effects according to the firstembodiment. In this case, although the areas of the upper electrodes112d become a little smaller than those in the first embodiment, it ispossible to make a reduction in area by chamfering the upper electrodes112a of rectangular shapes hardly affect the capacitance values of theferroelectric capacitors.

In addition, in the fourth embodiment of the invention, although thereis described the case in which four corners of the upper electrode 112aare chamfered in the memory cell array according to the firstembodiment, four corners of the upper electrode 112b or 112a may bechamfered in the memory cell array 100b or 110c according to the secondor third embodiment, and also in this case, the same effects as in thefourth embodiment are obtained.

Embodiment 5

FIG. 9 is a diagram for explaining a ferroelectric memory deviceaccording to a fifth embodiment of the present invention, and shows aplan configuration of upper electrodes of ferroelectric capacitorsconstituting the ferroelectric memory device.

In the figure, reference numeral 112e designates an upper electrodeconstituting a ferroelectric capacitor according to the fifthembodiment, and the plurality of upper electrodes 112e are arranged atpredetermined pitches on the lower electrode 111a extending along thefirst direction D1, along the second direction D2 perpendicular to thefirst direction D1, as in the first embodiment. In this case, the upperelectrode 112e is different from the upper electrode 112a of arectangular shape in the first embodiment, and its plan shape is ahexagonal shape having a direction D3 that forms an angle of 45° withrespect to the first direction D1 as its longitudinal direction.

That is, the hexagonal shape of the upper electrode 112e is constitutedby two lateral sides 112e₁ and 112e₂ that are parallel to the firstdirection D1 and opposite to each other, two longitudinal sides 112e₃and 112e₄ that respectively link to the lateral sides, and are parallelto the second direction D2 and opposite to each other, an oblique side112e₆ that links between the longitudinal side 112e₄ and the lateralside 112e₁, and an oblique side 112e₅ that links between thelongitudinal side 112e₃ and the lateral side 112e₂. At this time, theoblique sides 112e₆ and 112e₅ are parallel to the third direction D3.The other constructions are identical as in the first embodiment.

In the fifth embodiment with such a construction, since the plan shapeof the upper electrode 112e is a hexagonal shape having the direction D3that forms an angle of 45° with respect to the first direction D1, i.e.,a longitudinal direction of the lower electrode 111a, as itslongitudinal direction, a region of the upper electrode 112e that isaffected by deterioration of material quality of the ferroelectric layerat both side portions parallel to the first direction D1 can be reducedas in the first embodiment.

Further, in the fifth embodiment of the invention, since thelongitudinal direction of the upper electrode 112e is the obliquedirection D3 that forms an angle of 45° with respect to a widthdirection D2 (second direction) of the lower electrode, the length ofthe upper electrode 112e on the lower electrode 111a of the specifiedwidth size W₁ can be increased as compared with the first embodiment. Asa result, in the fifth embodiment, while occurrence of variations incharacteristics of the ferroelectric capacitors and characteristicchanges can be suppressed, the areas of the ferroelectric capacitors canbe increased to increase the capacitance values. More specifically, thecapacitance values of the ferroelectric capacitors can be increased byabout 25% of the values of the ferroelectric capacitors of the firstembodiment.

Furthermore, in the fifth embodiment, even when the distance between theopposite oblique sides of the adjacent upper electrodes 112e is set tobe, for example, the minimum process size, vacancy regions 116e areformed at portions of the lower electrode 111a at the vicinity of bothsides between the adjacent upper electrodes 112e. For example, wiringlayers comprising polysilicon, semiconductor elements or the like can bedisposed on the vacancy regions 116e, whereby the device area, i.e., thesubstrate area in the ferroelectric memory device, can be effectivelyutilized.

Embodiment 6

FIG. 10 is a diagram for explaining a ferroelectric memory deviceaccording to a sixth embodiment of the present invention, and shows aplan configuration of upper electrodes of ferroelectric capacitorsconstituting the ferroelectric memory device.

In the figure, reference numeral 112f designates an upper electrodeconstituting a ferroelectric capacitor according to the sixthembodiment, and the plurality of upper electrodes 112f are arranged atpredetermined pitches on the lower electrode 111a along the firstdirection D1, as in the first embodiment. In this case, the upperelectrode 112f is different from the upper electrode 112a of arectangular shape in the first embodiment, and has a plan shape F (FIG.10(c)) that is obtained by chipping one angle part f_(c) of arectangular shape F₀ (FIG. 10(b)) having the first direction D1 as itslongitudinal direction.

That is, the hexagonal shape F of the upper electrode 112f has alaterally long side 112f₁ and a first laterally short side 112f₂ thatare parallel to the first direction D1 and opposite to each other, and alongitudinally long side 112f₃ and a longitudinally short side 112f₄that are parallel to the second direction D2 perpendicular to the firstdirection D1 and opposite to each other. The laterally long side 112f₁and the longitudinally long side 112f₃ that link to each other at theends agree with a lateral side a₁ and a longitudinal side b₁ of therectangular shape F₀, respectively, and the ends of the laterally shortside 112f₂ and the longitudinally short side 112f₄ link to the otherends of the laterally long side 112f₁ and the longitudinally long side112f₃, respectively, and these sides are positioned on a longitudinalside a₂ and a lateral side b₂ of the rectangular shape F₀, respectively.Further, the shape F has a second laterally short side 112f₅ that hasone end linking to the other end of the longitudinally short side 112f₄and is parallel to the laterally long side 112f₁, and an oblique side112f₆ that has one end linking to the other end of the laterally shortside 112f₂ and the other end linking to the other end of the secondlaterally short side 112f₅, and that forms an interior angle of anobtuse angle with the laterally short side 112f₂.

In the sixth embodiment of the invention, arrangements shown in FIG.10(c) and arrangements that are obtained by making 180° revolution ofthe arrangements shown in FIG. 10(c) are alternatively disposed on thelower electrode 111a along the first direction D1. At this time, thesecond laterally short side 112f₅ of one of the adjacent upperelectrodes 112f and the laterally long side 112f₁ of the other arepositioned on the same line. Further, the distance between thelongitudinal sides of the adjacent upper electrodes 112f is set to bethe minimum process size S₂₂. The other constructions are identical asin the first embodiment.

In the sixth embodiment with such a construction, since the non-overlapwidth O₂₂, i.e., the distance between the laterally short side 112f₂ ofthe upper electrode 112f and the side 111a₂ of the lower electrode 111a,is narrowed at the laterally short side 112f₂ of, for example, the upperelectrode 112f (arrangement shown in FIG. 10(c)), close to the side111a₂ of the lower electrode 111a, the capacitance of the ferroelectriccapacitor can be increased. In addition, since the non-overlap widthO₂₁, i.e., the distance between the laterally long side 112f₁ of theupper electrode 112f and the side 111a₁ of the lower electrode 111a, iswiden at the laterally long side 112f₁ of the upper electrode 112f(arrangement shown in FIG. 10(c)) close to the side 111a₁ of the lowerelectrode 111a, the influence by deterioration of material quality ofthe ferroelectric layer at the side portions, which is formed on thelower electrode 111a, can be prevented from spreading over theferroelectric capacitor. Consequently, while occurrence of variations incharacteristics of the ferroelectric capacitors and characteristicchanges can be suppressed, the areas of the ferroelectric capacitors canbe increased to increase the capacitance values.

Further, in the sixth embodiment, since the ferroelectric capacitors arezigzag-arranged slightly without being arranged in a line, degree offreedom in a layout of the memory cell array, i.e., an arrangement ofthe memory transistors and the ferroelectric capacitors, and degree offreedom in an arrangement of the bit lines and the word lines can beimproved.

Furthermore, in the sixth embodiment, as the length of the firstlaterally short side 112f₂ of the upper electrode 112f that ispositioned at the vicinity of the side of the lower electrode 111a issmaller, the distance between the first laterally short side 112f₂ andthe side of the lower electrode 111a is shortened, whereby whilevariations in characteristics of the ferroelectric capacitors andcharacteristic changes can be prevented from being easily caused, thecapacitance values can be increased.

In addition, in the sixth embodiment, by chamfering four corners of theupper electrode 112f in which the interior angles in its plan shape are90° to make the interior angles larger than 90°, it is possible tofurther reduce the characteristic variations and further make thecharacteristic changes difficult with affecting the capacitance values.

Also in the sixth embodiment of the invention, on each region betweenthe lateral sides of the adjacent upper electrodes 112f in which thelongitudinally short sides 112f₄ are opposite to each other, and theside of the lower electrode 111a, i.e., a vacancy region 116f that issandwiched between the laterally long side 112f₁ of one of both of theupper electrodes 112f and the second laterally short side 112f₅ of theother, and the side of the lower electrode 111a, for example, a wiringlayer comprising polysilicon, a semiconductor element or the like can bedisposed, whereby the device area can be effectively utilized.

FIG. 11 illustrates a construction of a memory cell array 100f in whichthe vacancy regions 116f are effectively utilized as arrangement regionsof polysilicon layers constituting word lines.

In this memory cell array 100f, transistor regions 120f have a laterallylong shape having the first direction D1 as its longitudinal direction,and contact holes 105a on drain diffusion regions and a contact hole105b on a source diffusion region in each transistor region 120f arearranged in a line parallel to the first direction D1. On both sides ofthe transistor regions 120f arranged along the first direction D1, apair of word lines 123f₁ and 123f₂ is disposed along the first directionD1. The word lines 123f₁ and 123f₂ have gate portions 123f₁₁ and 123f₂₂constituting gate electrodes that are located between the source anddrain diffusion regions of each transistor region 120f. These gateportions 123f₁₁ and 123f₂₂ are formed unitedly with the word lines, andthe connection portions of the word lines and the gate portions and thesurrounding portions are disposed just below the vacancy regions 116f ofthe lower wirings 111a.

Usually, it is necessary that portions of the lower electrode 111a atwhich the ferroelectric capacitors are constituted be even, and no otherconstitutional materials can be disposed under these portions, but inthe sixth embodiment, since the vacancy regions 116f are formed atportions of the lower electrode 111a, except for the portions just belowthe upper electrodes 112f, for example, the parts of the word lines123f₁ and 123f₂ can be disposed under the vacancy regions 116f, wherebythe device area, i.e., the area on the substrate that is occupied by thememory cell array, can be effectively utilized.

In addition to the first to sixth embodiments described above,constructions of memory cell arrays that are obtained by combining theseembodiments can be realized.

In addition, although in the embodiments described above, there aredescribed the memory cell arrays constituting ferroelectric memorydevices as structures of ferroelectric capacitors, the ferroelectriccapacitor structures described for the respective embodiments can beapplied to circuits except a memory cell array.

Embodiment 7

FIGS. 12 and 13 are diagrams for explaining a ferroelectric memorydevice according to a seventh embodiment of the present invention, FIG.12 is a plan view illustrating a memory cell array constituting theferroelectric memory device, and FIG. 13 is a plan view illustrating aposition relation between upper electrodes and a lower electrodeconstituting ferroelectric capacitors in the memory cell array.

In the figures, reference numeral 100g designates a memory cell arrayconstituting a ferroelectric memory device according to the seventhembodiment. In this memory cell array 100g, a plan shape of each upperelectrode 112g is a shape that is obtained by forming notches 112g₁ atthe center portions of both sides along the second direction D2 of theupper electrode 112b in the second embodiment, and the otherconstructions are identical as in the second embodiment.

In the seventh embodiment with such a construction, the notches 112g₁can prevent deterioration of material quality of the ferroelectric layerdue to diffusion of impurities from the contact holes 104a that areformed on the upper electrodes 112a from spreading over portionscorresponding to the center of the upper electrodes 112a, to somedegree. That is, regions of the ferroelectric layer at whichdeterioration of material quality is caused by diffusion of impuritiesfrom the contact holes 104a can be prevented from spreading over thecenter portions of the upper electrodes 112b, thereby keeping wideregions of the ferroelectric layer at which no deterioration of materialquality is caused. Consequently, variations in characteristics as theferroelectric capacitors and characteristic deterioration can beeffectively suppressed.

INDUSTRIAL AVAILABILITY

As described above, a semiconductor device according to the presentinvention includes a first electrode of a stripe-shaped planconfiguration having a first direction as its longitudinal direction anda second direction perpendicular to the first direction as its widthdirection, and second electrodes are disposed on the first electrode viaa ferroelectric layer, thereby constituting ferroelectric capacitors, aplan configuration of the second electrode being a plan configuration ofthe size in the first direction and the size in the second directionbeing equal to each other, or a plan configuration of the size in thefirst direction being shorter than the size in the second direction, sothat the ratio of regions of the second electrodes that are positionedalong sides of the first electrode to the whole of the second electrodesis reduced, whereby the ferroelectric capacitors become structures thatare hardly affected by deterioration of material quality of theferroelectric layer at regions corresponding to the sides of the firstelectrode. As a result, variations in characteristics of theferroelectric capacitors can be suppressed and characteristic changesare hardly caused.

In addition, in this case, without reducing the areas of the secondelectrodes, the distances between the sides of the first electrode andthe sides of the second electrodes adjacent to the sides of the firstelectrode, respectively, can be shortened, whereby the layout area of amemory cell array can be reduced without decreasing the capacitances ofthe ferroelectric capacitors.

In a semiconductor device according to the present invention, theplurality of second electrodes are arranged along the first direction,opposite to the first electrode, and the arrangement intervals betweenthe adjacent second electrodes are set to be the process minimum size ofan opening pattern of a conductive material layer constituting thesecond electrodes, so that the layout area of a memory cell array onwhich the plurality of ferroelectric capacitors are located can bereduced.

In a semiconductor device according to the present invention, a planconfiguration of the second electrode is a polygonal configuration, andall the sizes of respective interior angles in the plan configuration ofthe second electrode are larger than 90°, so that it is possible toperform processing of the second electrodes with better reproducibility,whereby the variations in characteristics of the ferroelectriccapacitors and the characteristic changes can be further suppressed.

A semiconductor device according to the present invention includes firstelectrodes of a stripe-shaped plan configuration having a firstdirection as its longitudinal direction and a second directionperpendicular to the first direction as its width direction, and aplurality of second electrodes are disposed on the first electrodes viaferroelectric layers, thereby constituting a plurality of ferroelectriccapacitors, the plurality of second electrodes on the first electrodesbeing disposed in the form of a matrix in which the second electrodesare arranged lengthwise and breadthwise, so that the number offerroelectric capacitors per unit area on a memory cell array isincreased, resulting in a high-density layout on a substrate of thememory cell array.

In a semiconductor device according to the present invention, theplurality of second electrodes are arranged along the first direction,opposite to the first electrodes, and the arrangement intervals betweenthe adjacent second electrodes are set to be the process minimum size ofan opening pattern of a conductive material layer constituting thesecond electrodes, so that the layout area of the memory cell array onwhich the plurality of ferroelectric capacitors are located can bereduced.

A semiconductor device according to the present invention includes afirst electrode of a stripe-shaped plan configuration having a firstdirection as its longitudinal direction and a second directionperpendicular to the first direction as its width direction, and secondelectrodes are disposed on the first electrode via a ferroelectriclayer, thereby constituting ferroelectric capacitors, a planconfiguration of the second electrode being a plan configuration havinga direction between the first direction and the second direction as itslongitudinal direction, so that the ratio of regions of the secondelectrodes that are positioned along sides of the first electrode to thewhole of the second electrodes is reduced, whereby the ferroelectriccapacitors become structures that are hardly affected by deteriorationof material quality of the ferroelectric layer at regions correspondingto the sides of the first electrode. As a result, variations incharacteristics of the ferroelectric capacitors can be suppressed andcharacteristic changes are hardly caused.

In addition, in this case, without reducing the areas of the secondelectrodes, the distances between the sides of the first electrode andthe sides of the second electrodes adjacent to the sides of the firstelectrode, respectively, can be shortened, whereby the layout area of amemory cell array can be reduced without decreasing the capacitances ofthe ferroelectric capacitors.

In a semiconductor device according to the present invention, a planconfiguration of the second electrode is a polygonal configuration, andall the sizes of respective interior angles in the plan configuration ofthe second electrode are larger than 90°, so that it is possible toperform processing of the second electrodes with better reproducibility,whereby the variations in characteristics of the ferroelectriccapacitors and the characteristic changes can be further suppressed.

A semiconductor device according to the present invention includes afirst electrode of a stripe-shaped plan configuration having a firstdirection as its longitudinal direction and a second directionperpendicular to the first direction as its width direction, and secondelectrodes are disposed on the first electrode via a ferroelectriclayer, thereby constituting ferroelectric capacitors, a length of afirst side of the second electrode that is closest and opposite to afirst side of the first electrode parallel to the first direction beinglarger than a length of a second side of the second electrode that isclosest and opposite to a second side of the first electrode parallel tothe first direction, and the distance between the first side of thesecond electrode and the first side of the first electrode being longerthan the distance between the second side of the second electrode andthe second side of the first electrode, so that the longer one of thefirst and second sides of the second electrode is distant from the sideof the first electrode, whereby the ferroelectric capacitors are hardlyaffected by deterioration of material quality of the ferroelectric layerat regions corresponding to the sides of the first electrode. Further,the shorter one of the first and second sides of the second electrode isclose to the side of the first electrode, whereby the capacitances ofthe ferroelectric capacitors are increased. As a result, whilevariations in characteristics of the ferroelectric capacitors andcharacteristic changes can be suppressed, the areas of the ferroelectriccapacitors can be increased to increase the capacitance values.

In addition, in the present invention, the ferroelectric capacitors areeasily zigzag-arranged, whereby degree of freedom in a layout of amemory cell array, i.e., an arrangement of the memory transistors andthe ferroelectric capacitors, and degree of freedom in an arrangement ofbit lines and word lines can be simply improved.

In a semiconductor device according to the present invention, a planconfiguration of the second electrode is a polygonal configuration, andall the sizes of respective interior angles in the plan configuration ofthe second electrode are larger than 90°, so that it is possible toperform processing of the second electrodes with better reproducibility,whereby the variations in characteristics of the ferroelectriccapacitors and the characteristic changes can be further suppressed.

A semiconductor device according to the present invention has aplurality of memory cells respectively comprising ferroelectriccapacitors and memory transistors, a plurality of bit lines, a pluralityof word lines, and sense amplifiers, and includes first electrodes of astripe-shaped plan configuration having a first direction as itslongitudinal direction and a second direction perpendicular to the firstdirection as its width direction, and second electrodes are disposed onthe first electrodes via ferroelectric layers, thereby constituting theferroelectric capacitors, a plan configuration of the second electrodebeing a plan configuration of the size in the first direction and thesize in the second direction being equal to each other, or a planconfiguration of the size in the first direction being shorter than thesize in the second direction, so that the ratio of regions of the secondelectrodes that are positioned along sides of the first electrodes tothe whole of the second electrodes is reduced, whereby the ferroelectriccapacitors become structures that are hardly affected by deteriorationof material quality of the ferroelectric layers at regions correspondingto the sides of the first electrodes. As a result, variations incharacteristics of the ferroelectric capacitors can be suppressed andcharacteristic changes can be hardly caused.

In addition, in this case, without reducing the areas of the secondelectrodes, the distances between the sides of the first electrodes andthe sides of the second electrodes adjacent to the sides of the firstelectrode, respectively, can be shortened, whereby the layout area ofthe memory cell array can be reduced without decreasing the capacitancesof the ferroelectric capacitors.

A semiconductor device according to the present invention includes afirst electrode of a stripe-shaped plan configuration having a firstdirection as its longitudinal direction and a second directionperpendicular to the first direction as its width direction, secondelectrodes are disposed on the first electrode via a ferroelectriclayer, thereby constituting ferroelectric capacitors, and contact holesare formed in positions of an insulating film covering the surfaces ofthe second electrodes that are shifted from the center positions of thesecond electrodes to one side of the first electrode along the firstdirection, so that regions of the ferroelectric layer at whichdeterioration of material quality is caused by diffusion of impuritiesfrom the contact holes can overlap with regions at the sides of thefirst electrode at which deterioration of material quality is caused,thereby keeping wide regions of the ferroelectric layer at which nodeterioration of material quality is caused. Consequently, variations incharacteristics of the ferroelectric capacitors and characteristicdeterioration can be effectively suppressed.

A semiconductor device according to the present invention includes afirst electrode of a stripe-shaped plan configuration having a firstdirection as its longitudinal direction and a second directionperpendicular to the first direction as its width direction, secondelectrodes are disposed on the first electrode via a ferroelectriclayer, thereby constituting ferroelectric capacitors, the secondelectrodes having a structure in which the whole is divided into pluralelectrode portions by forming notches at predetermined sides, andwirings are connected to parts of the plural electrode portions throughcontact holes, so that the notches can prevent deterioration of materialquality of the ferroelectric layer due to diffusion of impurities fromthe contact holes that are formed on the second electrodes fromspreading over a wide range, to some degree. More specifically, wideregions of the ferroelectric layer at which no deterioration of materialquality is caused can be kept. Consequently, variations incharacteristics of the ferroelectric capacitors and characteristicdeterioration can be effectively suppressed.

What is claimed is:
 1. A semiconductor device comprising:a siliconsubstrate; an insulating film formed on the silicon substrate; a firstlower electrode disposed on the insulating film, the first lowerelectrode extending along a first direction and having a stripe-shapedplan configuration having a size in the first direction being longerthan that in a second direction perpendicular to the first direction;second upper electrodes disposed above the first electrode oppositethereto and having a plan configuration in which the size thereof in thefirst and second directions are shorter than those of the firstelectrode, and the size thereof in the first and second directions areequal to each other or the size in the first direction is shorter thanthe size in the second direction; a ferroelectric layer serving as acapacitance insulating film disposed between the first electrode and thesecond electrodes, wherein the first and second electrodes and theferroelectric layer therebetween constitute ferroelectric capacitors;and a contact hole disposed on a surface of each second electrode, eachsaid contact hole being shifted from the center of said surface to oneside along the first direction of the first electrode.
 2. Thesemiconductor device as defined in claim 1, wherein:the secondelectrodes are formed by a predetermined conductive material layer whichis patterned to have a plan configuration, and the plurality of secondelectrodes are arranged along the first direction; and the plurality ofsecond electrodes are respectively electrically independent, and theplurality of second electrodes, the first electrode and theferroelectric layer therebetween constitute electrically independentferroelectric capacitors.
 3. The semiconductor device as defined inclaim 1 wherein a plan configuration of the second electrode is apolygonal configuration, and all the sizes of respective interior anglesin the plan configuration of the second electrode are larger than 90°.4. A semiconductor device constituting a ferroelectric memory devicewith a plurality of memory cells respectively comprising ferroelectriccapacitors and memory transistors and arranged in the form of a matrix,cell plate lines for driving the ferroelectric capacitors, a pluralityof bit lines corresponding to respective memory cell columns, aplurality of word lines corresponding to respective memory cell rows,for selecting the memory transistors, and sense amplifiers connected tothe respective bit lines and amplifying data signals on thepredetermined bit lines, the semiconductor device comprising:a siliconsubstrate; an insulating film formed on the silicon substrate; firstlower electrodes disposed on the insulating film, the first lowerelectrodes extending along a first direction and having a stripe-shapedplan configuration having a size in the first direction being longerthan that in second direction perpendicular to the first direction, andconnected to the cell plate lines; second upper electrodes disposed onthe first electrodes opposite thereto and having a plan configuration inwhich the size thereof in the first and second directions are equal toeach other, or a plan configuration in which the size thereof in thefirst direction is shorter than the size in the second direction;ferroelectric layers serving as a capacitance insulating film disposedbetween the first electrodes and the second electrodes; wherein thefirst and second electrodes are the ferroelectric layers constitute theferroelectric capacitors; and a contact hole disposed on a surface ofeach second electrode, each contact hole being shifted from the centerof said surface to the one side along the first direction of the firstelectrode.
 5. A semiconductor device with ferroelectric capacitorscomprising:a silicon substrate; a first insulating film formed on thesilicon substrate; a first lower electrode disposed on the firstinsulating film constituting the ferroelectric capacitors, the firstlower electrode extending along a first direction and having astripe-shaped plan configuration having a size in the first directionbeing longer than a size in a second direction perpendicular to thefirst direction; second upper electrodes of the ferroelectric capacitorsdisposed on the first insulating film opposite to the first electrode,each second electrode having a plan configuration having a size in thefirst direction being equivalent to that in the second direction, or aplan configuration having a size in the first direction being shorterthan that in the second direction; a ferroelectric layer serving as acapacitance insulating film of the ferroelectric capacitors constitutingthe ferroelectric capacitors disposed between the first electrode andthe second electrodes; a second insulating film formed to cover thesurfaces of the second electrodes and having contact holes formed onpositions of the surfaces of the second electrodes that are shifted fromthe center positions to one side of the first electrode along the firstdirection; and wirings formed on the second insulating film andconnected to the second electrodes through the contact holes.